ASIC Design Verification Engineer

Role: ASIC Design Verification Engineer (DV/UVM) Location: Remote Job Type: W2 Contract Duration: 9-12 Months (Extension Possible) Job Description We are seeking experienced ASIC Design Verification Engineers with strong hands-on experience in System Verilog and UVM-based verification. Candidates will work on subsystem and full-chip integration verification for complex semiconductor designs. Required Technical Skills Strong experience in ASIC Design Verification (DV). Hands-on experience with S…